hym5321600a m-series 16mx32 bit fp dram module based on 16mx1 dram, 5v, 4k-refresh this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.02 / sep.97 ? 1997 hyundai semiconductor general description the hym5321600a m-series is a 16mx32-bit fast page mode cmos dram module consisting of thirty- two hy5116100b in 24/26 pin soj or tsop-ii on a 72 pin glass-epoxy printed circuit board. 0.1 m f and 0.01 m f decoupling capacitors are mounted for each dram. the hym5321600am /atm is tin plated and hym5321600amg /atmg is gold plated socket type single in- line memory module suitable for easy interchange and addition of 64m byte memory. features 72-pin simm fast page mode operation /cas-before-/ras, /ras-only, hidden and self refresh capability 4096 refresh cycles / 256ms (sl-part) 4096 refresh cycles / 64ms fast access time and cycle time speed trac tcac tpc 50 50ns 13ns 35ns 60 60ns 15ns 40ns 70 70ns 18ns 45ns ttl compatible inputs and outputs jedec standard pinout single power supply of 5.0v 10% low power dissip a tion max. self-refresh : 52.8mw (sl-part) max. battery back-up : 106mw (sl-part) max. cmos standby : 52.8mw (sl-part) 176mw max. ttl standby : 352mw max. operating speed power 50 19.4w 60 15.8w 70 14.1w ordering information part number speed features package plating hym5321600am 50/60/70 fp, 4k, 5v, soj simm tin hym5321600amg 50/60/70 fp, 4k, 5v, soj simm gold hym5321600a t m 50/60/70 fp, 4k, 5v, tsop simm tin hym5321600a t mg 50/60/70 fp, 4k, 5v, tsop simm gold
hym5321600a m-series rev.02 / sep.97 2 pin connection pin discription /ras0, /ras2 row address strobe /cas0~/cas3 column address strobe /we write enable a0~a11 address input dq0~dq31 data input/output pd1~pd4 presence detect vcc power (+5v) vss ground
hym5321600a m-series rev.02 / sep.97 3 pin assignments # name # name 1 vss 37 nc 2 dq0 38 nc 3 dq16 39 vss 4 dq1 40 /cas0 5 dq17 41 /cas2 6 dq2 42 /cas3 7 dq18 43 /cas1 8 dq3 44 /ras0 9 dq19 45 nc 10 vcc 46 nc 11 nc 47 /we 12 a0 48 nc 13 a1 49 dq8 14 a2 50 dq24 15 a3 51 dq9 16 a4 52 dq25 17 a5 53 dq10 18 a6 54 dq26 19 a10 55 dq11 20 dq4 56 dq27 21 dq20 57 dq12 22 dq5 58 dq28 23 dq21 59 vcc 24 dq6 60 dq29 25 dq22 61 dq13 26 dq7 62 dq30 27 dq23 63 dq14 28 a7 64 dq31 29 a11 65 dq15 30 vcc 66 nc 31 a8 67 pd1 32 a9 68 pd2 33 nc 69 pd3 34 /ras2 70 pd4 35 nc 71 nc 36 nc 72 vss
hym5321600a m-series rev.02 / sep.97 4 presence detect pins speed pd1 pd2 pd3 pd4 50 vss nc vss vss 60 vss nc nc nc 70 vss nc vss nc block diagram
hym5321600a m-series rev.02 / sep.97 5 absolute maximum ratings symbol parameter rating unit ta ambient temperature 0 to 70 c tstg storage temperature -55 to 150 c vin, vout voltage on any pin relative to vss -1.0 to 7.0 v vcc voltage on vcc relative to vss -1.0 to 7.0 v ios short circuit output current 50 ma pd power dissipation 32 w note : operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions (ta=0 c to 70 c) symbol parameter min. typ. max. unit vcc power supply voltage 4.5 5.0 5.5 v vih input high voltage 2.4 - vcc+1.0 v vil input low voltage -1.0 - 0.8 v note : all voltages are referenced to vss.
hym5321600a m-series rev.02 / sep.97 6 dc characteristics (t a =0 c to 70 c , vcc=5.0v 10% and vss=0v, unless otherwise noted.) speed/ max. current power 4k ref icc1 operating current /ras and /cas cycling trc=trc (min.) 50 60 70 3520 2880 2560 ma icc2 ttl standby current /ras=/cas 3 vih other inputs 3 vss 64 ma icc3 /ras-only refresh current /cas=vih, /ras cycling trc=trc (min.) 50 60 70 3620 2880 2560 ma icc4 fast page mode current /ras=vil, /cas, address cycling tpc=tpc (min.) 50 60 70 2560 2240 1920 ma icc5 cmos standby current /ras = /cas 3 vcc-0.2v sl-part 32 9.6 ma m a icc6 /cas-before- /ras refresh current /ras and /cas cycling trc=trc (min.) 50 60 70 3520 2880 2560 ma icc7 battery back-up current (sl-part) trc = 62.5 m s /cas = cbr cycling or 0.2v /oe & /we = vcc - 0.2v address = vcc-0.2v or 0.2v dq = vcc-0.2v, 0.2v or open tras 300ns tras 1 m s 11.2 19.2 ma ma icc8 self refresh current (sl-part) /ras & /cas = 0.2v other pins are same as icc7 9.6 ma symbol parameter test condition min. max. unit ili input leakage current (any input) vss vin vcc + 1.0 all other pins not under test = vss -320 320 m a ilo output leakage current (any input) vss vout vcc /ras & /cas at vih -10 10 m a vol output low voltage iol = 4.2ma - 0.4 v voh output high voltage ioh = -5.0ma 2.4 - v note 1. icc1, icc3, icc4 and icc6 depend on output loading and cycle rates( trc and tpc). 2. specified values are obtained with outputs unloaded. 3. icc is specified as an average current. in icc1, icc3, icc6, address can be changed only once while /ras=vil. in icc4, address can be changed maximum once while /cas=vih within one fast page mode cycle time tpc. 4. only / ras(max.) = 1 m s is applied to refresh of battery backup but tras(max.) = 10 m s is applied to normal functional operation. 5. icc5(max.) = 9.6m a , icc7 and icc8 are applied to sl-part only. symbol parameter test condition unit
hym5321600a m-series rev.02 / sep.97 7 ac characteristics (t a =0 c to 70 c, vcc=5.0v 10% and vss=0v, unless otherwise noted.) hym5321600a m-series # symbol parameter -50 -60 -70 unit note min. max. min. max. min. max. 1 trc random read or write cycle time 90 - 110 - 130 - ns 2 trwc read-modify-write cycle time 110 - 130 - 155 - ns 3 tpc fast page mode cycle time 35 - 40 - 45 - ns 4 tprwc fp mode read-modify-write cycle time 55 - 60 - 70 - ns 5 trac access time from /ras - 50 - 60 - 70 ns 4,5,6 6 tcac access time from /cas - 13 - 15 - 18 ns 4,5 7 taa access time from column address - 25 - 30 - 35 ns 4,6 8 tcpa access time from column precharge - 30 - 35 - 40 ns 4,9 9 tclz /cas to output low impedance 0 - 0 - 0 - ns 4 10 toff out buffer turn-off delay time from /cas 0 10 0 13 0 15 ns 7 11 tt transition time (rise and fall) 3 50 3 50 3 50 ns 2 12 trp /ras precharge time 30 - 40 - 50 - ns 13 tras /ras pulse width 50 10k 60 10k 70 10k ns 14 trasp /ras pulse width (fast page mode) 50 200k 60 200k 70 200k ns 15 trsh /ras hold time 13 - 15 - 18 - ns 16 tcsh /cas hold time 50 - 60 - 70 - ns 17 tcas /cas pulse width 13 10k 15 10k 18 10k ns 18 trcd /ras to /cas delay time 18 37 20 45 20 52 ns 5 19 trad /ras to column address delay time 13 25 15 30 15 35 ns 6 20 tcrp /cas to /ras precharge time 5 - 5 - 5 - ns 10 21 tcp /cas precharge time 10 - 10 - 10 - ns 22 tasr row address set-up time 0 - 0 - 0 - ns 23 trah row address hold time 10 - 10 - 10 - ns 24 tasc column address set-up time 0 - 0 - 0 - ns 25 tcah column address hold time 10 - 10 - 10 - ns 26 tral column address to /ras lead time 25 - 30 - 35 - ns 27 trcs read command set-up time 0 - 0 - 0 - ns 28 trch read command hold time referenced to /cas 0 - 0 - 0 - ns 8 29 trrh read command hold time referenced to /ras 0 - 0 - 0 - ns 8 30 twch write command hold time 8 - 10 - 10 - ns 31 twp write command pulse width 8 - 10 - 10 - ns 32 trwl write command to /ras lead time 13 - 15 - 18 - ns 33 tcwl write command to /cas lead time 13 - 15 - 18 - ns
hym5321600a m-series rev.02 / sep.97 8 ac characteristics (continued) hym5321600a m-series # symbol parameter -50 -60 -70 unit note min. max. min. max. min. max. 34 tds data-in set-up time 0 - 0 - 0 - ns 9 35 tdh data-in hold time 10 - 10 - 10 - ns 9 36 tref refresh period (4096 cycles) - 64 - 64 - 64 ms refresh period (sl-part) - 256 - 256 - 256 ms 37 twcs write command set-up time 0 - 0 - 0 - ns 10 38 tcwd /cas to /we delay time 13 - 15 - 20 - ns 10 39 trwd /ras to /we delay time 50 - 60 - 70 - ns 10 40 tawd column address to /we delay time 25 - 30 - 35 - ns 10 41 tcsr /cas set-up time (cbr cycle) 5 - 5 - 5 - ns 42 tchr /cas hold time (cbr cycle) 10 - 10 - 15 - ns 43 trpc /ras to /cas precharge time 5 - 5 - 5 - ns 44 tcpt /cas precharge time (cbr counter test) 15 - 20 - 25 - ns 45 tcpwd /we delay time from /cas precharge 30 - 35 - 40 - ns 10 46 trhcp /ras hold time from /cas precharge 30 - 35 - 40 - ns 47 twrp /we to /ras precharge time(cbr cycle) 10 - 10 - 10 - ns 48 twrh /we to /ras hold time (cbr cycle) 10 - 10 - 10 - ns 49 trass /ras pulse width (self refresh) 100 - 100 - 100 - m s 50 trps /ras precharge time (self refresh) 90 - 110 - 130 - ns 51 tchs /cas hold time (self refresh) -50 - -50 - -50 - ns
hym5321600a m-series rev.02 / sep.97 9 note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cbr refresh cycles instead of 8 /ras only refresh cycles are required. 2. vih(min.) and vil(max.) are reference levels for measuring timing of input signals. transition times are measured between vih(min.) and vil(max.) 3. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (ta = 0 to 70 c) is assured. 4. measured at voh=2.4v and vol=0.4v with a load equivalent to 2 ttl loads and 100pf. 5. operation within the trcd (max.) limit insures that trac(max.) can be met. trcd(max.) is specified as a reference point only. if trcd is greater than the specified trcd(max.) limit, then access time is controlled by tcac 6. operation within the trcd (max.) limit insures that trac(max.) can be met. trad(max.) is specified as a reference point only. if trad is greater than the specified trad(max.) limit, then access time is controlled by taa 7. toff(max.) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 8. either trch or trrh must be satisfied for a read cycle .. 9. these parameters are referred to /cas leading edge in early write cycles and to /we leading edge in read-modify- write cycles. 10. twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs ?? twcs(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if tcwd 3 tcwd (min.), trwd 3 trwd(min.) and tcpwd 3 tcpwd(min.), then the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. capacitance (t a =25 c, vcc=5.0v 10% , vss=0v and f = 1mhz, unless otherwise noted.) symbol parameter typ. max. unit cin1 input capacitance (a0~a11) - 192 pf cin2 input capacitance (/ras0, /ras2) - 128 pf cin3 input capacitance (/cas0~/cas3) - 72 pf cin4 input capacitance (/we) - 256 pf cdq data input /output capacitance (dq0~dq35) - 22 pf
hym5321600a m-series rev.02 / sep.97 10 package information 72 pin single in-line memory module (soj /tsop-ii mounted)
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